1. Field of the invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory used as a VRAM in an image processing.
2. Description of related art
A semiconductor memory used as a VRAM in an image processing ordinarily comprises a function of inputting/outputting a random access data and a function of inputting/outputting a serial data. A typical example of this semiconductor memory is shown in FIG. 4.
This semiconductor memory first includes, as external input/output ports, a RAM timing control signal input port Prtc, an address input port Pad, a random data input/output port Prdt, a SAM timing control signal input port Pstc, a serial data input/output port Psdt, a serial mask data input port Psmd. An internal construction includes a RAM array which is a multi-bit memory cell array composed of memory cells arranged in a two-dimensional array having rows and columns, a row address buffer circuit 2 and a row address decoder 3 for obtaining a row address indicating a position of a row in the RAM array 1, a column address buffer circuit 4 and a column address decoder 5 for obtaining a column address indicating a position of a column in the RAM array 1, a SAM array 8 composed of linearly-arranged memory cells of the same number as the number of memory cells in a column direction, a serial address counter 10 operating to sequentially count up or down in synchronism with a serial clock SC supplied through the SAM timing control signal port Psc in order to sequentially read/write the memory cells of the SAM array 8 in accordance with a column address of the RAM array 1, a serial address decoder 9 for decoding the value of the serial address counter 10 to internally generate an address of the SAM array 8, a mask register 7 for holding data indicating the position of a bit(s) to be masked when the RAM array 1 is to be written through the external input/output port, a read/write controller 6 for controlling the writing into the RAM array 1 in accordance with the position of the bit(s) to be masked from the writing, indicated by the data of the mask register 7, a serial mask register 13x for holding data indicating the position of a bit(s) to be masked when a write transfer from the SAM array 8 to the RAM array 1 is carried out, a write transfer gate 12 for controlling the write transfer from the SAM array 8 to the RAM array 1 in accordance with the position of the bit(s) to masked from the write transfer, indicated by the serial mask register 13x, a read transfer gate 11x for controlling the data transfer from the RAM array 1 to the SAM array 8, and a timing generator 14x for controlling operation timings of the RAM array 1 and the SAM array 8.
As regards the above mentioned semiconductor memory, first, a method for carrying a random read/write operation to the RAM array 1 will be described.
In order to carry out the reading/writing to a memory cell at an arbitrary position in the RAM array 1, a row address and a column address are supplied simultaneously. The row address is supplied through the address input port Pad from an external, and then, is latched in the row address buffer circuit 2 in response to a row address latch timing signal RLT generated in the timing generator 14x on the basis of a RAS (row address strobe) signal supplied through the RAM timing control signal input port Prtc. The row address latched in the row address buffer circuit 2 is decoded by the row address decoder 3 and then is supplied to the RAM array 1.
On the other hand, the column address is also supplied through the address input port Pad from the external, and then, is latched in the column address buffer circuit 4 in response to a column address latch timing signal CLT generated in the timing generator 14x on the basis of a CAS (column address strobe) signal supplied through the RAM timing control signal input port Prtc. The column address latched in the column address buffer circuit 4 is decoded by the column address decoder 5 and then is supplied to the RAM array 1. Thereafter, the read/write operation is executed to the memory cell within the RAM array designated by the decoded values of the row address decoder 3 and the column address decoder 5, through the random data input/output port Prdt.
This semiconductor memory also has a write inhibit function for carrying a write masking in units of a bit, using the data of the mask register 7, when the writing is carried out to the RAM array 1.
Next, a serial read method for reading the data from the RAM array 1 through the SAM array 8 will be described.
When the serial reading is carried out, first, the data of the RAM array 1 is transferred to the SAM array 8. This transfer is executed for the data on the row address designated by the row address buffer circuit 2 and the row address decoder 3 associated to the RAM array 1. Therefore, this transfer is executed in a cycle requiring the same time as that of the random read/write cycle. The data transferred to the SAM array 8 is sequentially read out through the serial data input/output port Psdt in synchronism with the serial clock signal SC supplied from the SAM timing control signal input port Pstc, asynchronously with the RAM timing control signal. This data reading of this SAM array 1 can ordinarily be executed in the cycle, which is about 1/6 of the read/write cycle of the RAM array 1, by not multiplexing the address, and by constructing the memory in a SRAM structure so that when the memory cell of the SAM array is read out, a sense operations required at the time of reading the memory cell of the RAM array 1 is no longer necessary.
Furthermore, a serial write method for writing the data into the RAM array 1 through the SAM array 8 will be described.
In a serial writing operation, data to be written is first sequentially written into the SAM array 8 through the serial data/input port Psdt in synchronism with the serial clock signal SC supplied through the SAM control signal port Pstc. The data written in the SAM array 8 is then transferred to the RAM array 1 so as to be written into memory cells within the RAM array 1. At this time, by supplying information (SMD) of a bit(s) or column(s) not to be masked, from the serial mask input port Psmd to the serial mask register 13x, the transfer to the memory cells at a special bit(s) or a column address(es) within the RAM array 1 can be masked.
Referring to FIG. 5, there is shown a circuit diagram of a specific circuit example of a data transfer system of this semiconductor memory. In FIG. 5, SDB designates a serial data bus, and SRWC indicates a serial read/write control signal. SMEP and SMEN denote a SAM activation enable signal, and SMDw shows mask data controlled by the write transfer control signal. RTC designates a lump read transfer control signal, and RRWC indicates a random read/write control signal. RDB denotes a random data bus, and SEP and SEN show a sense amplifier enable signal. WL designates a word line.
By supplying the information of the bit(s) or column(s) to be masked, from the serial mask input port Psmd to the serial mask register 13x, the transfer to the memory cell(s) on a special bit(s) or column address(es) within the RAM array 1 is masked. As a means for controlling this masking, a write transfer control signal WTC is provided for each bit or column to be masked.
In an image processing using this semiconductor memory, in order to partially rewrite the data of the SAM array 8 with the data of the RAM array 1, for example by allocating data including R(red), G(green), B(blue) and brightness to respective bits and by rewriting the data of R, G and B by the data of the RAM while fixing only the data of the brightness, it is necessary that the information of the column not to be rewritten by the data of the RAM is written into the serial mask register 13x, and thereafter, data is transferred once from the SAM array 8 to the RAM array 8 at the row address to be used for the partial rewriting, while using the serial mask function based on the information of the serial mask register 13x, and then, the data on the memory cells on the same row address in the RAM array 1 is re-transferred to the SAM array 8. Alternatively, it is necessary to write the data to be left in the SAM array 8, to the RAM array 1 at the row address to be used for the partial writing, in a random writing mode, and then, to transfer the data on the memory cells on the same row address in the RAM array 1 to the SAM array 8.
As mentioned above, in this prior art semiconductor memory, in order to partially rewrite the data of the SAM array 8 with the data of the RAM array 1, it is necessary to carry out either of the following two methods: In the first method, after the information of the column not to be rewritten with the data of the RAM array 1 is written into the serial mask register 13x, data is transferred once from the SAM array 8 to the RAM array 8 at the row address to be used for the partial rewriting, while using the serial mask function based on the information of the serial mask register 13x, and then, the data on the memory cells on the same row address in the RAM array 1 is re-transferred so the SAM array 8. The second method is to write the data to be left in the SAM array 8, to the RAM array 1 at the row address to be used for the partial writing, in a random writing mode, and then, to transfer the data on the memory cells on the same row address in the RAM array 1 to the SAM array 8. Therefore, the processing time becomes large, and it becomes one cause for remarkably lowering a high speed processing capability inherently required for the VRAM. In particular, in the VRAM having no serial write function, only the second method can be adopted, so that the larger the number of data to be held in the SAM array is, the processing capability abruptly drops. In either case, it is a problem that the content held in the RAM array 1 is rewritten.
Furthermore, since the serial mask register 13x is written in the serial write operation, the RAM timing control signal input port Prtc operating asynchronously cannot be used, and therefore, it is necessary to provide the serial mask data input port Psmd as an interface to the external. As a result, the chip area is increased by provision of the port, and therefore, the integration density drops. This is a problem.